PC-30-02K60藥片檢測

        Table 8-4. Trigger and Integration Time Controlled by Two bbbbbs Label Debbbbbbion Min Typ Max ti Integration time duration 5 μs – – td1 TRIG2 rising to integration period start delay – 100 ns – td2 TRIG1 rising to integration period stop delay – 1.3 μs – tt Integration period stop to read-out start delay – 1 μs – th TRIG1 and TRG2 hold time (pulse high duration) 1 μs – – td1 td2 ti tt Integration N Integration N+1 Readout N-1 Readout N

        Output Data Timing This timing corresponds to the bbbbb data of the Camera bbbb interface. The camera output data are not detailed here because fully compliant with the Camera bbbb standard (serial high-speed interface). Table 8-4. Trigger and Integration Time Controlled by Two bbbbbs Label Debbbbbbion Min Typ Max ti Integration time duration 5 μs – – td1 TRIG2 rising to integration period start delay – 100 ns – td2 TRIG1 rising to integration period stop delay – 1.3 μs – tt Integration period stop to read-out start delay – 1 μs – th TRIG1 and TRG2 hold time (pulse high duration) 1 μs – – td1 td2 ti tt Integration N Integration N+1 Readout N-1 Readout N TRIG1 TRIG2 Table 8-5. Output Data Timing Label Debbbbbbion Min Typ Max tp bbbbb falling edge to output clock propagation delay – 7 ns – td STROBE to synchronized signals delay -5 ns – +5 ns

      In case of multi-cameras synchronization (means more than one camera on one acquisition board): 

     ? the "master" camera will provide DATA, STROBE and LVAL signals to the acquisition board. The others will only provide DATA.

     ? the external clock CLK_IN must be bbbbb on each cameras to guaranty perfect data synchronization. 

     ? the trigger(s) bbbbb (TRIG1 and/or TRIG2) must be bbbbb on each cameras. It is recommended to synchronize the rising edge of these signals on the CLK_IN falling edge.

     ? cables must be balanced between each cameras (same quality, same length) to ensure perfect cameras synchronization.

     ? the CLK_IN frequency must be equal to the two CCD register frequency. It means that the user shall use either H=2 (2 taps at CLK_IN data rate) or H=10 (1 tap at 2xCLK_IN data rate). Using H=1 clock mode will provide LVAL jitter on the "slave" camera. 

     ? Only "triggered and integration time controlled" (M=3 or M=4) can be used. These modes ensure perfect readout phase starting for each cameras.